Worst-Case Timing Analysis of Cycle-Stealing DMA I/O Tasks

A DMA controller that operates in the cycle-stealing mode is allowed to transfer data only when the CPU does not need the system bus. Thus, the execution time of a cycle-stealing DMA I/O task depends on the sequence of instructions executing concurrently with it. This paper describes a method for bounding the worst-case execution time (WCET) of a cycle-stealing DMA I/O task. We rst deene the task model. We next describe several properties of instruction sequences that can execute concurrently with a cycle-stealing DMA I/O task. Based on these properties we develop a recursive formula to compute the WCET of the DMA I/O task. The recursive formula gives the basis of a dynamic programming method to nd the WCET of the DMA I/O task. We conducted a simulation experiment to evaluate the performance of the dynamic programming method.